A phase locked loop (PLL) generates a periodical output signal. This output signal is responsive to a reference signal. A PLL can reconstruct a reference clock signal, can divide a reference clock signal or multiply a reference clock signal.
FIG. 1 illustrates prior art PLL 10. PLL 10 includes oscillator 20, frequency divider 30, phase detector 40 and control circuit 50. Oscillator 20 is connected to control circuit 50 and to frequency divider 30. Phase detector 40 is connected between frequency divider 30 and control circuit 50.
Oscillator 20 oscillates to provide output signal So 22 having output frequency Fo 24 in response to a control signal Sc 52 provided by control circuit 50. Frequency divider 30 generates a feedback signal Sf 32 that has a feedback frequency Ff 34 that can be a fraction of output frequency Fo 24. Phase detector 40 receives feedback signal Sf 32 and reference signal Sr 12 and outputs phase error signal Spe 42 that represents a phase difference between feedback signal Sf 32 and reference signal Sr 12. Control circuit 50 receives phase error signal Spe 42 and generates control signal Sc 52.
The power consumption of PLL 10 is responsive to output frequency Fo 24. When output frequency Fo 24 is high PLL 10 consumes a substantial amount of power. This power consumption empties a power source that supplies power to PLL 10.
locked loop